1. Technical Field
Embodiments described herein relate to integrated circuit memory and testing memory. More particularly, embodiments described herein relate to the built-in self tests for memory and methods and logic circuits for testing memory.
2. Description of Related Art
Logging errors during high speed tests of memories using built-in self tests (BISTs) for integrated circuit memory (e.g., RAM or SRAM) may be process intensive. For example, a typical BIST for memory may run through the entire memory and it is possible that some memory failures may not be captured during the test. In some cases, memory failures may not be captured due to counter size limitations (e.g., the number of failures exceeds the size of the counter capturing the failures).
One example of a typical memory test (e.g., memory BIST) is a SONE (stop on nth error) test. In the SONE test, a start, capture, stop, start sequence is used to test the memory. After starting the test, the test is stopped at every error and error data is dumped from the memory. The test is then restarted after dumping the memory error information including any addressing information for the memory error. Thus, for n number of errors in the memory, the test is running n number of times. Running the test through the memory in this repeated manner is time consuming and increases the chances for inconsistent error capture information during the test.
Additionally, identifying the address of each memory error (e.g., determining address information) during the BIST may be complicated. For example, memory addresses may be cryptic in nature and there may be numerous steps to identifying a specific address for each memory error found during a single memory test. Correctly identifying each and every address may be difficult and error prone for a specific address for each memory error since memory addresses have complicated scrambling of address lines. Additional complexity may be introduced by the error data, which have further scrambling and multiplexing.